The present disclosure relates generally to integrated circuit design tools, and, in particular, to hierarchical integrated circuit repartitioning.
In designing integrated circuits using very large scale integration (VLSI), thousands of transistor-based circuits can be integrated into a single package. A VLSI design may be used for developing a variety of integrated circuits, such as application specific integrated circuits (ASICs), microprocessors, microcontrollers, memory devices, and the like. VLSI designs are typically developed using either a flat or hierarchical physical design. In a flat design, where all circuits are routed at the same level, a design tool can layout a circuit interconnection topology faster due to fewer placement constraints as compared with a hierarchical design employing multiple levels. Another approach to VLSI design is to use a flexible hierarchical design that establishes regional constraints for circuit placement and allows for regions to overlap. Denser VLSI designs that incorporate a larger number of circuits within a single chip often require some form of hierarchical design to fit within the physical dimensions of the chip.
Even though a hierarchical design may be desired for the final design of a VLSI chip, an initial VLSI design often treats circuits within the design as existing within the same level of hierarchy (pseudo-flat), in order to simplify analysis. For example, a design may include a parent level (top level) and one or more child levels. Each level may include multiple entities, such as multiple children entities on the same child level, e.g., a modular design. Timing analysis can be performed faster if the design is initially viewed as existing at a common level, e.g., placing the source and sink pins of children at the same location as the driving and receiving circuit pins of the children (also known as “inboard” pins). Using this approach enables timing analysis to be performed early in the design process, before the full hierarchy is designed. By adding interconnecting elements, such as latches, to a single level of the design, the impact of changes is minimized for various aspects of the design and verification process, e.g., simulation, integration, and timing analysis.
As the design matures, interconnecting elements between children are often placed at the parent level, while driving and receiving circuits are incorporated at the child level. This approach maintains the child level design while only modifying the parent level to adjust for timing and signal drive strength constraints for signals routed between child entities. Since the levels of hierarchy are physically stacked over each other, the parent entity may have very little silicon reservation inside of a child as well as limited use of lower level metal where interconnecting elements are placed and routed. When an edge pin implementation is used for a signal on a child, any signals from overlapping parent entities that enter or exit the child can have extra wire introduced to them. In many cases, the extra wire will degrade the timing and wiring solutions, causing performance to diverge from the original design. Accordingly, there is a need in the art for repartitioning between parent and child levels in hierarchical integrated circuit design.